Openings for Design and Verification At Infosys

Hi,

We have a requirement for a subcontractor for Infosys. The details are as follows:

1. Skill: Design & Verification
2. Duration Of Hiring:Sub Contract
3. Offshore/Onsite: Offshore
4. Years of experience: 3-7 years
5. Extension Possible: Yes

6. Work Location: Bangalore

7: Job Description:

Design and Verification:

Must have:

·         Good knowledge of digital design

·         Good knowledge of ASIC design flow

·         Hands on knowledge of complete ASIC Front-end verification flow – Verification planning to closure.

·         Good knowledge of Verilog/VHDL

·         Hands on knowledge of HVLs (Specman/System Verilog)

·         Worked on methodologies like VMM, OVM, eRM

·         Basic knowledge of C++       

·         Good team player and ability to work with  stakeholders like RTL team, DFT team and Physical Design team

·         Good hands on knowledge of Gate level  simulations (with back annotated delay values)

·         Good hands on knowledge of Planning and execution of IP level and fullchip verification.

Nice to have:

·         Knowledge on ARM based SoC fullchip verification

·         Experience on Low Power verification

·         Experience on Timing verification

·         Domain Knowledge of protocols like DDR3, GDDR5, PCIe, PCI, PCIX, RapidIO, AMBA protocols, OCP

-      Toolset: NC, VCS, Modelsim, Verdi, Spyglass

Send ur cv to   srilakshmi@primusglobal.com  and subject line - Refered by RSK